Verilog / FPGA implementation of the ben-eater 8-bit breadboard CPU
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| rtl | ||
| tests | ||
| .clangd | ||
| .gitignore | ||
| LICENSE | ||
| Makefile | ||
| readme.md | ||
beneater-fpga
An fpga / verilog implementation of ben eater's 8-bit breadboard CPU.
License
This project is licensed under AGPL-3.0-or-later. For more information see the LICENSE file, or alternative online under https://www.gnu.org/licenses/.
Building
TODO
Tests
This repository uses verilator for it's tests. All verilator tests are make targets, beginning with sim_. For an overview of all of them, run make help