- Typst 100%
| .gitignore | ||
| chap_cpu_ctrl.typ | ||
| chap_instr.typ | ||
| chap_interrupt.typ | ||
| chap_overview.typ | ||
| chap_registers.typ | ||
| chap_virt_mem.typ | ||
| instr_notes.txt | ||
| main.typ | ||
| readme.md | ||
Home of Drakrúni
Wellcome traveler and young smithy! You found your way into the sacred halls of the Drakrúni ISA's documentation repository! Here, the Alfǫdr's Forge collects all documentation of their in-house ISA for all of the world to see.
License
This project is licensed under AGPL-3.0-or-later. You should have recieved a copy of the License together with this file, named LICENSE. If not, please see the terms of the license here: https://www.gnu.org/licenses/agpl-3.0.en.html
Core concepts and design decisions
The core concept of this ISA is to find an bridge between RISC and CISC architecture, sometimes jokingly referred to as MISC (just me then? well...). It should both support powerfull instructions while keep being simple to learn and implement. Ideally, it also should be efficent enough to run larger machines with it. To facillitate this, it was choosen that there is an core ISA which has multiple flavors, depending on complexity, space and energy requirements, and a few other factors.